1. Field
This disclosure generally relates to electronics. More particularly, the disclosure relates to Integrated Circuits (“ICs”).
2. General Background
As the geometry of the transistor becomes smaller, current manufacturing processes are having difficulty adhering to the specifications for manufacturing the transistor. For example, a design of a transistor may utilize a particular timing, e.g., six hundred MHz. However, once the design of the IC is manufactured at a fabrication plant, the resulting IC may not meet the design specification of six hundred MHz. For example, the manufactured IC may have a timing of only five hundred seventy five MHz.
Accordingly, testing is performed to determine which path, or possibly paths, inside the manufactured IC does not meet the timing of the design specification. Utilizing the modern day pins inside the IC to perform the testing is ineffective because these pins can not run at the timing of the design specification. For example, the pins may run at three hundred MHz where as the timing of the design specification may be six hundred MHz. Price and technology limitations are contributing factors to the inefficacy of the pins in testing the IC.
Alternatively, utilizing the phase-locked loop (“PLL”) clock inside the IC allows for testing that is commensurate with the timing of the design specification. As opposed to the pins that may run up to three hundred MHz, the PLL clock can run at a much higher speed such as six hundred MHz. As a result, the PLL clock can be utilized to test the IC at-speed, i.e., the full speed at which the IC is intended to run. However, current approaches do not effectively control the PLL to output only a few clock cycles so that the part of the IC not meeting the timing can be tested.